Buildhardwarewith clarity

AI-native tooling for digital design and verification.

01 — READ ANY DESIGN

Point at a folder. Get the whole picture

Veritas reads your project, elaborates every file through Slang, and draws the schematic. Real bit widths, evaluated parameters, actual cross-module nets. Drill into any block, inspect ports and signals, then edit the source right there. Save, and the schematic redraws around your change.

Software moved on. Hardware got left behind

A software engineer works in one environment: write, test, debug, ship, all AI-assisted. A hardware engineer stitches together a dozen disconnected tools: editor, simulator, waveform viewer, linter, FPGA tools. Every handoff loses context. Every bug means re-explaining the design to a tool that doesn't remember it. The result is weeks lost re-deriving what your own design is doing.

Legacy code editor

$0+

per seat, per year

for a full commercial IC design flow

Source: DeepPCB — The EDA Pricing Problem

The tools were never built for you

Software has almost no barrier to entry: anyone can build and ship with a laptop and free tools. By contrast, a full commercial IC-design toolchain can cost more than $100,000 per seat per year, putting industry-standard workflows beyond the reach of many students, startups, and small teams. The next great hardware engineer might be sitting at a laptop right now, unable to even access the tools that would let them try. Access is the bottleneck, not talent.

FULL SYSTEMVERILOG VIA SLANG
INTERACTIVE SCHEMATICS
CYCLE-ACCURATE SIMULATION
100% LOCAL

Every layer, visible.

From RTL to waveform, Veritas makes your entire design legible.

SCHEMATIC

See your RTL as a schematic.

RTL schematic view
SIMULATION

Cycle-accurate simulation.

Cycle-accurate simulation waveform
LINT

Real-time lint as you type.

Real-time lint warning showing a 16-bit to 8-bit truncation
CDC

Clock-domain crossing analysis.

Clock-domain crossing hazard
VERITAS AGENT

An agent that does real work.

✓read_file
fifo.sv
✓run_lint
3 findings
✓patch_file
fifo.sv
✓run_simulation
PASS

Gets the job done with the same tools you use.

TWO MODES

Build and understand

Build
Tutor
Build

Creates, edits, lints, simulates, and verifies your RTL.

Tutor

Read-only. Explains by pointing at code, schematics, FSMs and waveforms.

WalkthroughStep 2 of 4
UART receiver — start-bit detect

Same agent, two personas — Build changes your RTL; Tutor only explains it.

PRIVACY

Your RTL never leaves your machine.

Run local models so nothing leaves your machine.

VERSION CONTROL

Diff your RTL, visually.

a1b2c3d▸HEAD~1 → HEAD
Visual RTL diff between two commits
1 added1 removed2 modified

Schematic

See the design, not just text

Veritas parses your RTL into a living hierarchy: connectivity graphs, cross-module signal tracing, and clock-domain mapping that update as you edit, so you always see structure instead of scrolling through thousands of lines.

Simulation & verification

Run cycle-accurate simulation with Icarus

Run cycle-accurate simulation inline, inspect waveforms beside your RTL, catch issues with real-time lint, extract FSMs automatically, and verify datapaths against golden models — without leaving the workspace.

Veritas simulation waveform and verification view

Meet Veritas Your hardware engineering agent

AI agents

An agent that uses the same tools as you

Two personas: one that edits, simulates and verifies your design, another one that explains by pointing at the schematic, FSM, and waveform.

thinking…

THE AGENT

One agent. The whole flow.

Design, simulation, synthesis — one session, one design context, from first module to final netlist.

1

Design

Reads your modules, edits RTL, runs Slang and Verilator lint, and traces clock-domain crossings that no simulation will ever catch.

2

Simulate

Writes testbenches, runs them through Icarus Verilog, then reads the waveform back to reason about why it failed.

3

Synthesize

Runs Yosys, reads resource counts and critical paths, explains the latch you didn't mean to infer, then optimizes the RTL to reduce area and shorten the critical path, re-synthesizing to prove the win.

Your model. Your choice.

One workflow.
Every frontier model.

Veritas works with the models you trust. Switch providers seamlessly. Stay in control.

No cloud. No keys.

Run it all
on your own machine.

Point Veritas at Ollama or LM Studio and the same agent runs entirely on your hardware. No API key. No upload.

AMD Vivado

Integrated FPGA Workflow

Veritas runs your RTL through AMD Vivado on the part you actually target — synthesis, placement, routing — and brings back LUT and flip-flop counts, worst-case slack, and the path that's holding you back.

One button, no Tcl
Sealed, traceable runs
Timing in plain English

AMD and Vivado are trademarks of Advanced Micro Devices, Inc. Veritas is not affiliated with or endorsed by AMD.

Let's build something real

Ready to bring clarity to your hardware workflow? Reach out and we'll get back to you within a day

veritas.founders@gmail.com
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